Software Engineer I

About this role

Batch: 2023/2024/2025/2026. Responsibilities: - Engage in the logic design and verification of digital IPs, CPUs, peripherals, and sub-systems across various VLSI domains. - Create and implement innovative designs and testbenches that are highly scalable, configurable, and efficient. - Strong hands-on experience with UVM testbench development is highly valued. Qualifications: - Minimum of 1+ years of experience with Bachelor's or Master's in Engineering - Solid understanding of electrical engineering concepts, Digital Electronics, and VLSI design concepts - Excellent communication, problem-solving and analytical skills. - Ability to work independently and in a team. - Good understanding in one or more of the following areas: a) Computer architecture b) Logic design c) Circuit design and semiconductor devices d) Programming languages such as C/C++, Java, Python/Perl, Tcl, Haskell e) Hardware Description Language like Verilog, System Verilog or VHDL